Prior art processors and computer systems may be limited in the number of accesses to a particular cache or group of caches that can be concurrently managed. One prior art technique used to combat this problem has been the use of an inclusive cache structure whose cache entries correspond to the cache entries of one or more processor core-specific caches, such as level 1 (L1) caches.
In other words, prior art multi-core processors and/or multi-processor computer systems have attempted to reduce cache access conflicts within core caches by simply directing some of the cache accesses to a shared inclusive cache structure, such as a last level cache (LLC), that contains all of the cache entries of the processor cores or agents to which the inclusive cache structure corresponds. In the case of a cache access from a core within a multi-core processor, however, the core will typically attempt to access data first from its own cache and then resort to the shared cache. The shared inclusive cache structure is sometimes referred to as a “cache filter”, as it shields core caches from excessive cache accesses, and therefore bus traffic, from other agents by providing the requested data to these agents from the inclusive cache instead of the core's cache.
The prior art technique of using a cache structure, such as an LLC, for servicing cache requests from various agents is helpful in allowing requesting agents to obtain the data they need without resorting to a cache of a processor core, for example, if the data is not exclusively owned or modified by a particular processor core. To the extent that an agent, such as a processor or processor core owns the cache line of its cache that the requesting agent is trying to access, a cache structure, such as an LLC, can allow the requesting agent to obtain the data it is requesting rather than waiting for the owning agent to share the data.
However, other conflicts can occur when using an LLC to service cache requests from external agents and processor cores. FIG. 1, for example, illustrates two cores attempting to access the same cache line of an LLC as an external agent. Particularly, in FIG. 1, core 0 has initiated a core cache request to a line in core 1's cache (via an LLC snoop) at substantially the same time as an external agent is snooping the LLC. In some cases, a snoop may need to be done by the LLC to core 1's cache (“cross snoop”) in order to fulfill the core request of core 0, resulting in at least four different opportunities for a conflict to occur between the external agent's snoop of the LLC and the cross snoop.
The first potential conflict, “conflict window A” in FIG. 1, occurs before a core request look-up to the LLC cache and before the cross-snoop from the LLC to the other core is made. A second potential conflict, “conflict window B” in FIG. 1, occurs when there is a cross-snoop pending during a time when a snoop of the LLC from an external agent occurs. A third potential conflict, “conflict window C” in FIG. 1, occurs during a time after the cross-snoop has been initiated and the requesting core is awaiting the cross-snooped data and an external agent snoops the LLC. Finally, a fourth potential conflict, “conflict window D” in FIG. 1, occurs when the cross-snooped data has been returned to the requesting core and the LLC has yet to be updated with the cross-snoop data and an external agent snoops the LLC.
The prior art problem depicted in FIG. 1 is exacerbated as the number of processor cores or other bus agents increases in the system. For example, the conflicts depicted in FIG. 1 may double in a multi-core processor containing four cores instead of the two illustrated in FIG. 1. Similarly, as the number of processors increase in a computer system, so does the number of cross-snoops to any particular core cache, thereby increasing the number of conflicts that can occur during an LLC snoop by an external agent.
Cache conflicts, such as those depicted in FIG. 1, can have adverse effects on processor performance as resolving the conflicts takes multiple processing cycles. Accordingly, the number of agents or the number of cores within a multi-core computer system may be limited in prior art processor and/or computer systems.